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Pin No. Pin Name I/O Function
48 CLK O
Command serial data transfer clock signal output to the CXD2587Q (IC101)
49 XLT O
Command latch pulse output to the CXD2587Q (IC101) “L” active
50 DATA O
Command serial data output to the CXD2587Q (IC101)
51 SQCLK O
SENS serial data reading clock and subcode Q data reading clock signal output to the CXD2587Q
(IC101)
52 SUBQ I
Subcode Q data input from the CXD2587Q (IC101)
53 NC O
Not used (open)
54 SENS I
Internal status monitor input from the CXD2587Q (IC101) “H” active
55 OUTSW I
Inputs the loading in/out detect switch (S801) detection signal “L” active
56 RMIN I
Remote control signal input from the remote control receiver (IC601) “L” active
57 AFADJ I
Setting terminal for the test mode “L”: AFADJ mode, Normally: fixed at “H”
58 FLLT O
Serial data latch pulse output to the FL driver (IC701) “L” active
59 NC O
Not used (open)
60 KBCIN O
Serial data transfer clock signal output terminal Not used (open)
61 SCOR I
Subcode sync (S0+S1) detection signal input from the CXD2587Q (IC101) “H” active
62 T.SENS1 I
Disc table flag detect sensor (IC802) input terminal
63 T.SENS2 I
Disc table flag detect sensor (IC803) input terminal
64 T.SENS3 I
Disc table home position detect sensor (IC801) input terminal
65 ICSW O
Enable signal output to the LA5616 (IC506) Used for the BD section reset “H” active
66 RFSW O
RF AGC hold control signal output to the CXA2568M (IC103) “H” active
67 INSW I
Inputs the loading in/out detect switch (S801) detection signal “L” active
68 to 71 D3 to D6 I/O
Two-way data bus with the static RAM (IC502)
72 VDD —
Power supply terminal (+5V)
73 NC (VDD) —
Not used (connected to power supply (+5V) line)
74 D7 I/O
Two-way data bus with the static RAM (IC502)
75 to 77 D2 to D0 I/O
Two-way data bus with the static RAM (IC502)
78 to 80 A0 to A2 O
Address signal output to the static RAM (IC502)