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is sampled and held on capacitor C502 and
buffered by 4/4 U508. The A/D conversion is done
by successive approximation using comparator
U514 to compare the sampled and held signal with
known outputs of U505, a 12 bit DAC with a
precision reference. Note that the output of U506,
an 8 bit DAC is summed with the output of U505.
This 8 bit DAC corrects for offset errors which can
accumulate as analog voltages pass through
buffers, S/H amps, and comparators. These
offsets are measured after each unit is
manufactured, and values to compensate for
these offsets are placed in the unit's ROM. The
polarity of the offset-corrected 12 bit DAC is set by
2/4 U511 and the SIGN bit yielding 13 bits of
resolution from -10.24 to +10.24 volts.
D/A's
In addition to providing reference voltages for A/D
conversion, the DAC output voltage may be
multiplexed by U507 to one of eight sample and
hold amplifiers which provide analog output and
control voltages. The microprocessor refreshes
each S/H amplifier every few milliseconds to
prevent droop. Two of these outputs are available
as general programmable outputs on the rear
panel. Two are used to program the band pass
filter and the reference oscillator phase shift. One
output is subtracted from the lock-in output in
U508 to provide a variable offset and another is
the rms noise output. Two outputs are not used.
Expand
Amplifier 3/4 U511 is the X10 expand amplifier.
U516 selects the display and output, either the
output of U511 or one of the DAC outputs.
Overload is detected by 1/4 and 2/4 U515 and the
signal monitor is driven by 3/4 U515.
Front Panel
There are 62 led's on the front panel controlled by
8 serial-in, parallel-out shift registers. All 8 shift
registers are written to simultaneously and 8
consecutive write operations are required to set
the LED's. The liquid crystal displays are
managed by the display controllers, U601 and
U602. Exclusive-or gates U605 and U606 drive
the left over segments. Octal latch U604 provides
the logic bits for these extra segments as well as
the keyboard row strobes. U603 reads the switch
closures as the rows are scanned.
Microprocessor Control
The microprocessor, U701, is a Z80A CPU
clocked at 4 Mhz. 16K bytes of firmware are
stored in the ROM, U702. U703 is a 2K byte static
RAM, backed-up by a lithium battery. A power-
down standby circuit, Q701, preserves the RAM
contents when the power is turned off. The
battery has a life of 5-10 years. The CPU has
power-up and power-down resets to prevent
erroneous execution during turn-on or short sags
in the line voltage.
U704 is a 3-channel counter. One channel
generates the baud rate for the RS232 interface
while the other two are used to measure the
frequency or period of the reference oscillator.
U709 provides a gate pulse to counter 0.
Multiplexer U708 selects whether the gate is a
single period of the reference (period
measurement) or a gate of known duration
(frequency measurement). Counter 1 is a
programmable divide by N counter whose output
is either counted for one period of the reference,
or, generates the gate pulse during which
reference pulses are counted.
I/O addresses are decoded by U705, U706, and
U707. The microprocessor controls the lock-in
functions through I/O ports U714-U721. U713
generates an interrupt to the CPU every 4 msec to
keep the microprocessor executing in real time.
RS232 Interface
The RS232 interface uses an 8251A UART, U801,
to send and receive bytes in a bit serial fashion.
Any standard baud rate from 300 to 19.2K baud
may be selected with the configuration switches.
The X16 transmit and receive clock comes from
counter 2 of U704. The RS232 interface is
configured as DCE so that a terminal may be
connected with a standard cable. When a data
byte is received by the UART, the RxRDY output
interrupts the CPU to prevent the data from being
overwritten.
GPIB Interface
The interface to the GPIB is provided by U802, an
MC68488 General Purpose Interface Adapter
(GPIA). The GPIB data and control lines are
buffered by drivers U808 and U811. Because the
GPIA uses a 1 MHz clock, wait states are provided
by U805 to synchronize I/O transactions with the 4
MHz CPU. The GPIA interrupts the CPU