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I/O
—
O
O
I
I
O
I
O
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—
I/O
I
I
I
O
O
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—
I
I
I
I
I
Description
Ground
External RAM address output
Not used
Test data input “L” = normal “H” = test (Connecting to ground)
PLL input frequency select “L” = 256Fs “H” = 128Fs (Connecting to ground)
PLL output frequency select “L” = 768Fs “H” = 1024Fs (Connecting to ground)
Master clock input
Master clock output (Not used)
Ground
+3.3V
Ground for PLL cell
VDD for PLL cell
PLL output/test clock input
PLL cell oscillation enable “L” oscillation enable “H” oscillation stop (Connecting to ground)
Test data input “L” = normal “H” = test (Connecting to ground)
Frequency counter input (Connecting to ground)
LRCK0 divider output
BCK0 divider output
Ground
+3.3V
BCK input
BCK input
LRCK input
LRCK input
Serial data input
Pin Name
VSS0
EA13 – EA15
EA16
TSTA
PLDIVF
PLDIVB
CLKI
CLKO
VSS1
VDD0
AV SS
AV DD
PLLCK
XPLLEN
TST
LRCT
LROUT
BKOUT
VSS2
VDD1
BCK0
BCK1
LRCK0
LRCK1
SIA – SID