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Rev.1.00 2003.05.08
page 3 of 23
M65881AFP
BLOCK DIAGRAM
M
C
K
S
E
L
F
s
o
C
K
O
F
s
o
I
X
f
s
o
O
U
T
X
f
s
o
I
N
S
F
L
A
G
OUTR1
OUTL1
OUTR2
OUTL2
Sampling
Rate Converter
Gain Control
DATA
BCK
LRCK
S
C
D
T
S
C
S
H
I
F
T
S
C
L
A
T
C
H
18
17
16
2
41
39
4
I
N
I
T
N
S
P
M
U
T
E
X
f
s
i
I
N
Clock
Generator
( Primary )
Clock
Generator
( Secondary )
INIT/MUTE
Serial
Control
25
26
T
E
S
T
2
24
HPOUTR1
HPOUTL1
HPOUTR2
HPOUTL2
33
29
27
31
PWM
T
E
S
T
1
15
14
11 12 13
21
23
2210
6
36
∆Σ
S⇒P