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Rev.1.00 2003.05.08
page 18 of 23
M65881AFP
3. System2 Mode
No setting bits means "Don't care".
Table 3-1 DC dithering selection at ∆Σ block
Table 3-2 AC dithering selection at ∆Σ block
Table 3-3 Setting of ∆Σ block operating
The selection of primary master clock ( bit3: IMCKSEL )
L … 256fsi
H … 512fsi ( "512fsi" are divided into half "256fsi" and operate as primary master clock. )
Re-synchronization (bit6: SYNC)
Refer to Page9 in details on re-synchronous operation.
Resynchronization process starts by SYNC rise edge, therefore SYNC level must be fixed to
"L" just before SYNC operation.
"Enable" of a XfsoOUT output (bit7:XfsoOEN)
"L" ... Clock Output (enable)
"H"… "L" fixed (disable)
bit
Flag name
19 DCDSEL0
20 DCDSEL1
DC dithering 0.1%
H
L
DC dithering 0.2%
L
H
DC dithering 0.4%
H
H
bit
Flag name
22 ACDSEL0
Non dithering
don't care
L23 ACDSEL1
AC dithering A
L
H
AC dithering C
L
L
L24 ACDSEL2 L H
AC dithering E
L
H
H
bit
Flag / Pin code name
16 NSSPEED
16fso,6bit
L
16fso,5bit
L
16fso, 5bit
X
32fso, 5bit
H
L
( Secondary master clock
1024fso)
Pin MCKSEL
L
( Secondary master
clock 1024fso)
L
( Secondary master
clock 1024fso)
H
( Secondary master clock
512fso)
Non dithering
L
L
bit Flag name Functional Explanation H L
INIT
1 MODE1 Mode settiing1 "H" fixed
-
2 MODE2 Mode setting2 "L" fixed
-
3 IMCKSEL
Input master clock Selection 512fsi 256fsi
L
4
-
5
-
6 SYNC Re-synchronization
L
7 XFsoOEN
XfsoOUT pin output "enable". disable enable
L
8 ASYNCEN2
Asynchronous Detection Flag for secondary Side
enable disable
L
9 CHSEL L/R inversion of PWM output pin
active non-active
L
10 DRPOL
∆Σ Block : Rch Input Phase
Negative phase Positive phase
L
11 SRCRST
Sampling Rate Converter Reset
active
non-active
L
12 CHRSEL L/R inversion of PWM output pin
active non-active
L
13 GIMUTE Zero Mute at Gain Control Input Clock
active non-active
L
14 NSPMUTE Duty 50% Mute for PWM Output
active non-active
L
15 PGMUTE G_MUTE of PWM Output Data
active non-active
L
16 NSSPEED ∆Σ Block : Operating Speed 32fso 16fso
L
17 NSOBIT
∆Σ Block : Setting of Output bit number 5bit (31value) 6bit (63 value)
L
18 DCDRPOL ∆Σ Block : Rch Phase of AC dithering Negative phase Positive phase
L
19 DCDSEL0
L
20 DCDSEL1
L
21 ACDRPOL ∆Σ Block : Rch Phase of AC dithering Negative phase Positive phase
L
22 ACDSEL0
L
23 ACDSEL1
L
24 ACDSEL2
L
L ->H : Resynchronization
∆Σ Block : DC dithering selection
∆Σ Block : AC dithering selection
Refer to Table 3-1
Refer to Table 3-2
L17 NSOBIT H X H