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Philips Semiconductors Application note
AN1651Using the NE/SA5234 amplifier
2
1991 Oct
Author: L. Hadley
I. SUMMARY
The NE/SA5234 is a unique low-voltage quad operational amplifier
specifically designed to operate in a broadly diverse environment. It
is an enhanced pin-for-pin replacement for the LM324 category of
devices. Supply conditions can range from 1.8V to 6.0V with a
resultant current drain of 2.8mA,-700µA per op amp.
Most notable are the input and output dynamic range characteristics
of the individual op amps. The common-mode input voltage can
actually exceed the positive and negative supply rails by 250mV
with no danger of output latching or polarity reversal. In addition, the
output of each op amp will swing to within 50mV of the supply rails
over the full supply range.
The frequency related characteristics are also above average for
low voltage devices in this class. Internal unity gain compensation
makes the NE5234 very resistant to any tendency to oscillate in low
closed-loop gain configurations. Even so, a unity-gain bandwidth of
2.5MHz is retained. Slew rate is 0.8V/µs and each op amp will
settle to a 1% of nominal level within 1.4µs.
II. DETAILED DESCRIPTION
Input Stage
The input differential amplifier consists of a compound transistor
structure of parallel NPN and PNP transistors which account for the
unique over-drive characteristics of the NE5234. Referring to Figure
1, it is seen that the NPN pair, Q1 and Q2, allow the input to
operate in the common-mode input voltage range of 1V above V
EE
.
This region is designated the N-mode region in Figure 3a.
Operation in the common-mode range below 1V transfers the input
stage into the P-mode of operation.
In the N-mode operating condition, collector current from Q1 and Q2
is summed in the output emitter node of Q10 and Q12 respectively.
Q1’s base is the non-inverting input and Q2’s base the inverting
input node for the amplifier.
V
CC
R10
R11
VB2
Q10
Q12
VB1
IB1
Q2
Q4Q3
Q5
SWITCH
Q9
R8 R9
Q6
Q7
Q8
I
P
I
N
V
BIAS
IN(–)
(+)
+
–
Q2
SL00630
Figure 1. NE5234 Input Stage
Linear operation between the two modes is governed by a current
steering circuit consisting of Q5,6 and 7 in conjunction with voltage
reference VB1. Operation in the
N-region of the common-mode range will automatically cause Q5 to
transfer the IB1 current source to Q7 and the NPN transistor pair Q1
and Q2. Operation below the 1V level at the inputs allows the
current from IB1 to be fed directly to Q3 and Q4 emitters giving them
priority in processing the signal and linearizing their transfer
function. (The sum of the NPN and PNP input pair currents remain
constant.)
Operation in the common-mode range near the positive supply rail
would normally cause the input stage NPN transistor’s base
collector junction to become forward biased (base current flow
directly to the collector circuit) reversing the collector current flow
direction. In a conventional op amp, this would have the adverse
effect of reversing the output signal polarity as the operating region
is traversed by the input signal. (see Figure 2)
To prevent this from occurring, large geometry diode-connected
transistors are cross-connected to the opposite NPN collector, (Q1,
Q2). This current, in turn, is summed at the emitter of Q12 pulling it
above the V
CC
rail voltage and preventing polarity reversal. The
inverse condition occurs when Q2 is driven above the positive rail,
with Q10 emitter being pulled up and signal polarity preserved. (See
Figure 1)