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MAX9777/MAX9778
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
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15
Early STOP Conditions
The MAX9777 recognizes a STOP condition at any
point during the transmission except if a STOP condi-
tion occurs in the same high pulse as a START condi-
tion (Figure 5). This condition is not a legal I
2
C format;
at least one clock pulse must separate any START and
STOP condition.
REPEATED START Conditions
A REPEATED START (S
r
) condition may indicate a
change of data direction on the bus. Such a change
occurs when a command word is required to initiate a
read operation. S
r
may also be used when the bus
master is writing to several I
2
C devices and does not
want to relinquish control of the bus. The MAX9777 ser-
ial interface supports continuous write operations with
or without an S
r
condition separating them. Continuous
read operations require S
r
conditions because of the
change in direction of data flow.
Acknowledge Bit (ACK)
The acknowledge bit (ACK) is the ninth bit attached to
any 8-bit data word. The receiving device always gen-
erates ACK. The MAX9777 generates an ACK when
receiving an address or data by pulling SDA low during
the night clock period. When transmitting data, the
MAX9777 waits for the receiving device to generate an
ACK. Monitoring ACK allows for detection of unsuc-
cessful data transfers. An unsuccessful data transfer
occurs if a receiving device is busy or if a system fault
has occurred. In the event of an unsuccessful data
transfer, the bus master should reattempt communica-
tion at a later time.
Slave Address
The bus master initiates communication with a slave
device by issuing a START condition followed by a 7-bit
slave address (Figure 6). When idle, the MAX9777
waits for a START condition followed by its slave
address. The LSB of the address word is the
Read/Write (R/W) bit. R/W indicates whether the master
is writing to or reading from the MAX9777 (R/W = 0
selects the write condition, R/W = 1 selects the read
condition). After receiving the proper address, the
MAX9777 issues an ACK by pulling SDA low for one
clock cycle.
The MAX9777 has a factory-/user-programmed
address. Address bits A6–A2 are preset, while A0 and
A1 is set by ADD. Connect ADD to either V
DD
, GND,
SCL, or SDA to change the last 2 bits of the slave
address (Table 2).
SCL
SDA
STOP START
SCL
SDA
ILLEGAL
STOP
START
LEGAL STOP CONDITION
ILLEGAL EARLY STOP CONDITION
Figure 5. Early STOP Condition
S A6A5A4A3A2A1A0R/W
Figure 6. Slave Address Byte Definition
ADD CONNECTION I
2
C ADDRESS
GND 100 1000
V
DD
100 1001
SDA 100 1010
SCL 100 1011
Table 2. MAX9777 I
2
C Slave Addresses