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12 BLOCK DIAGRAMS
12.1 System Processor Mode
Page 24
Source
Select
& Sum
1
2
3
4
5
6
7
8
Input Channels A to D Output Channels 1 to 8
UX8800 BLOCK DIAGRAM
System Processor Mode
U-Net Out
1 to 32
U-Net Out
Assign
U-Net Out
1 to 32
10 EQ
Filters
10 EQ
Filters
10 EQ
Filters
10 EQ
Filters
10 EQ
Filters
10 EQ
Filters
10 EQ
Filters
10 EQ
Filters
10 EQ
Filters
10 EQ
Filters
10 EQ
Filters
10 EQ
Filters
Source
Select
Source
Select
Source
Select
Source
Select
Source
Select
Source
Select
Source
Select
Source
Select
X-Over
X-Over
X-Over
X-Over
X-Over
X-Over
X-Over
X-Over
Gain &
Polarity
Gain &
Polarity
Gain &
Polarity
Gain &
Polarity
Gain &
Polarity
Gain &
Polarity
Gain &
Polarity
Gain &
Polarity
Mute
Mute
Mute
Mute
Gain &
Polarity
Gain &
Polarity
Gain &
Polarity
Gain &
Polarity
Meter
Meter
Meter
Meter
Meter
Meter
Meter
Meter
Meter
Meter
Meter
Meter
Limiter
Limiter
Limiter
Limiter
Limiter
Limiter
Limiter
Limiter
Mute
Mute
Mute
Mute
Mute
Mute
Mute
Mute
U-Net Out
Assign
U-Net Out
Assign
U-Net Out
Assign
U-Net Out
Assign
U-Net Out
Assign
U-Net Out
Assign
U-Net Out
Assign
U-Net Out
Assign
U-Net Out
Assign
U-Net Out
Assign
U-Net Out
Assign
Output
Connectors
1 to 8
AES/EBU
Receiver
B
C
D
1
2
A
AES A Ch 1
AES A Ch 2
AES C Ch 1
AES C Ch 2
U-Net In
1 to 32
AES/EBU
Receiver
Input
Connectors
A to D
U-Net
Connectors
INPUT NOTES:
Input connector B [D] is disabled
when A [C] is set for AES/EBU use.
Analog A
Analog D
Analog C
Analog B
Source
Select
& Sum
Source
Select
& Sum
Source
Select
& Sum
Delay
Delay
Delay
Delay
Alignment
Delay
Alignment
Delay
Alignment
Delay
Alignment
Delay
Alignment
Delay
Alignment
Delay
Alignment
Delay
Alignment
Delay
ADC
ADC
U-Net
In / Out
DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC