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TMPR3901F
218
The relationship among the clocks is shown in the table below.
Master clock
(FCLK)
RF [1:0]
Processor
clock
HALF*
System clock
(SYSCLK)
00 1 H 1
L 1/2
01 1/2 H 1/2
1 L 1/4
10 1/4 H 1/4
L 1/8
11 1/8 H 1/8
L 1/16