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r
WAVEFORMS
1
IC501 1 TE
2
3
IC501 ed (RF)
IC501 rs (FE)
Approx.
12 mVp-p
Approx.
1.2 Vp-
p
Approx.
10 mVp-p
Note on Schematic Diagram: MAIN SECTION
• All capacitors are in µF unless otherwise noted. pF: µµF
50 WV or less are not indicated except for electrolytics
and tantalums.
• All resistors are in Ω and
1
/
4
W or less unless otherwise
specified.
•
f
: internal component.
Note: The components identified by mark 0 or dotted
line with mark 0 are critical for safety.
Replace only with part number specified.
• : B+ Line.
• Power voltage is dc 1.5V and fed with regulated dc power
supply from battery terminal.
• Voltages and waveforms are dc with respect to ground
under no-signal conditions.
no mark : PLAY
• Voltages are taken with a VOM (Input impedance 10 MΩ).
Voltage variations may be noted due to normal produc-
tion tolerances.
• Waveforms are taken with a oscilloscope.
Voltage variations may be noted due to normal produc-
tion tolerances.
• Circled numbers refer to waveforms.
• Signal path.
F : Analog
J : Digital
* Replacement of IC601 used in this set requires a special
tool.
• The voltage and waveform of CSP (chip size package)
cannot be measured, because its lead layout is different
from that of conventional IC.
Note on Printed Wiring Boards: MAIN SECTION
• X : parts extracted from the component side.
• : Pattern from the side which enables seeing.
(The other layers' patterns are not indicated.)
Caution:
Pattern face side: Parts on the pattern face side seen from the
(Side B) pattern face are indicated.
Parts face side: Parts on the parts face side seen from the
(Side A) parts face are indicated.
• Main boards is four-layer pritnted board.
However, the patterns of layer 2 and 3 have not been
included in this diagrams.
* Replacement of IC601 used in this set requires a special
tool.
• Lead Layouts
Lead layout of
conventional IC
surface
CSP (chip size package)
VOLT/DIV : 5 mV AC
TIME/DIV : 1 µsec
VOLT/DIV : 0.5 V AC
TIME/DIV : 0.5 µsec
VOLT/DIV : 5 mV AC
TIME/DIV : 1 µsec
SECTION 6
DIAGRAMS