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HP 8560 E-SERIES
FAST
ADC
(OPTION
007)
w59
BLOCK DIAGRAM
FROM
A2J15
1
P/O A3
I
I
I
I
I
I
I
I
I
I
I
I
I
INTERFACE ASSEMBLY
JlOl
-----
1
PEAK,
I
Tql6
I
QE”
Q
a5
w---w
L--W-
VIDEO BUFFER
1
J102
1
Xl
I
L -----
JlO5
PANEL
0
MS3
L!>
J3
6
MHz TTL
OUT
ANALOG BUS
VIDLO
ENABLE
FROM SHEET 3,
H
0
TP9
1
?p
----
TP14
U
VIDEO MUX
19
I
I
t
I
L-
L---
---
JlOJ
MS5
Q
TP17
2
*
0
C
CLOCK AND
SAMPLE RATE
GENERATOR
A CPU
I0
INTERFACE
h
AND CONTROL
I
10
D TRIGGER
VIDEO
I NPUT
REG I STERS
I
L
V
iDE0
-----
TRIG
I
L
P2-P7
aI
137e
FIGURE 8-3. FAST ADC (OPTION 007) BLOCK DIAGRAM