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Revision History
REV ECN Number Approved
DOCUMENT CONTROL #:
13
BlockDiagram.sch
A
DATE: 22-Oct-2003
ADS8402/ADS8412EVM Block Diagram
6446998
-IN
+IN
EXT_REF
B_CS
B_RD
B_CONVST
B_BYTE
B_RESET
BUSY
DB[15...0]
Analog-to-Digital Converter
ADC Data Bus
Analog Input
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
P1
B_DB[15...0]
DB[15...0]
CS
RD
CONVST
BYTE
RESET
B_BUSY
BUSY
B_CS
B_RD
B_CONVST
B_BYTE
B_RESET
+AVCC
+VA
-VA
+BVDD
DC_CS
A0
A1
A2
INTc
Power & Digital Buffer
J2
B_DB[15...0]
DB[15..0]
B_DB0
B_DB1
B_DB2
B_DB3
B_DB4
B_DB5
B_DB6
B_DB7
B_DB8
B_DB9
B_DB10
B_DB11
B_DB12
B_DB13
B_DB14
B_DB15
J4
+BVDD
TP11
TP14
TP13
TP12
CS
RD
CONVST
BYTE
RESET
B_BUSY
ADC Control
12
34
56
78
9
11
10
12
J3
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
P3
TP9
TP10
1 2
3 4
5 6
7 8
9 10
J1
+VA -VA
+5VD
AGND
+5VA
DGND
+3.3VD
W1
DC_CS
A0
A1
A2
INTc
Lijoy Philipose
Lijoy Philipose
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
P2
Parallel Control