6Registers
www.ti.com
Registers
TheTCP2containsseveralmemory-mappedregistersaccessibleviatheCPU,QDMA,andEDMA3.A
peripheral-busaccessisfasterthananEDMA3-busaccessforisolatedaccesses(typicallywhen
accessingcontrolregisters).EDMA3-busaccessesareintendedtobeusedforEDMA3transfersandare
meanttoprovidemaximumthroughputto/fromtheTCP2.
ThememorymapislistedinTable3,includingallTCP2memories(systematicandparity,interleaver,
harddecisions,apriori,andextrinsic).Alladdressesprovidedareoffsetaddresses.FortheTCP2base
dataaddressandTCP2basecontroladdress,seethedevice-specificdatamanual.
Table3.TCP2Registers
TCP2DataOffsetTCP2ControlRegister/Memory
AddressOffsetAddressAbbreviationNameSee
0x00000TCPPIDTCPPeripheralIdentificationRegisterSection6.1
0x00000TCPIC0TCPInputConfigurationRegister0Section6.2
0x00004TCPIC1TCPInputConfigurationRegister1Section6.3
0x00008TCPIC2TCPInputConfigurationRegister2Section6.4
0x0000CTCPIC3TCPInputConfigurationRegister3Section6.5
0x00010TCPIC4TCPInputConfigurationRegister4Section6.6
0x00014TCPIC5TCPInputConfigurationRegister5Section6.7
0x00018TCPIC6TCPInputConfigurationRegister6Section6.8
0x0001CTCPIC7TCPInputConfigurationRegister7Section6.10
0x00020TCPIC8TCPInputConfigurationRegister8Section6.11
0x00024TCPIC9TCPInputConfigurationRegister9Section6.12
0x00028TCPIC10TCPInputConfigurationRegister10Section6.13
0x0002CTCPIC11TCPInputConfigurationRegister11Section6.14
0x00030TCPIC12TCPInputConfigurationRegister12Section6.15
0x00034TCPIC13TCPInputConfigurationRegister13Section6.16
0x00038TCPIC14TCPInputConfigurationRegister14Section6.17
0x0003CTCPIC15TCPInputConfigurationRegister15Section6.18
0x00040TCPOUT0TCPOutputParametersRegister0Section6.19
0x00044TCPOUT1TCPOutputParametersRegister1Section6.20
0x00048TCPOUT2TCPOutputParametersRegister2Section6.21
0x0004CTCPEXETCPExecuteRegisterSection6.22
0x00050TCPENDTCPEndiannessRegisterSection6.23
0x00060TCPERRTCPErrorRegisterSection6.24
0x00068TCPSTATTCPStatusRegisterSection6.25
0x00070TCPEMUTCPEmulationRegisterSection6.26
Table4.TCP2RAMs
TCP2DataOffsetRegister/Memory
AddressAbbreviationNameAddressRangeLength
0x10000X0Data/SysandParityMemory0x10000-0x243FF0x00014400
0x30000W0ExtrinsicMem00x30000-0x351FF0x00005100
0x40000W1ExtrinsicMem10x40000-0x451FF0x00005100
0x50000I0InterleaverMemory0x50000-0x5a1FF0x0000A200
0x60000O0Output/DecisionMemory0x60000-0x60a7F0x00000A20
0x70000S0ScratchPadMemory0x70000-0x70aFF0x000006E0
0x80000T0BetaStateMemory0x80000-0x80FFF0x00000A00
0x90000C0CRCMemory0x90000-0x90FFF0x000001C0
SPRUGK1–March2009TMS320C6457Turbo-DecoderCoprocessor225
SubmitDocumentationFeedback
