S1C63000 CORE CPU MANUAL EPSON 53
CHAPTER 4: INSTRUCTION SET
RETI
RETS
RL %A
%B
[%X]
[%X]+
[%Y]
[%Y]+
RR %A
%B
[%X]
[%X]+
[%Y]
[%Y]+
SBC %A,%A
%A,%B
%A,imm4
%A,[%X]
%A,[%X]+
%A,[%Y]
%A,[%Y]+
%B,%A
%B,%A,n4
%B,%B
%B,imm4
%B,[%X]
%B,[%X],n4
%B,[%X]+
%B,[%X]+,n4
%B,[%Y]
%B,[%Y],n4
%B,[%Y]+
%B,[%Y]+,n4
[%X],%A
[%X],%B
[%X],%B,n4
[%X],imm4
[%X],0,n4
[%X]+,%A
[%X]+,%B
[%X]+,%B,n4
[%X]+,imm4
[%X]+,0,n4
[%Y],%A
[%Y],%B
[%Y],%B,n4
[%Y],imm4
[%Y],0,n4
[%Y]+,%A
[%Y]+,%B
[%Y]+,%B,n4
[%Y]+,imm4
[%Y]+,0,n4
SET [00addr6],imm2
[FFaddr6],imm2
SLL %A
%B
1111111111001
1111111111011
1000011110010
1000011110110
1000011101000
1000011101001
1000011101010
1000011101011
1000011110011
1000011110111
1000011101100
1000011101101
1000011101110
1000011101111
110001111000X
110001111001X
110001100i3i2i1i0
1100011100000
1100011100001
1100011100010
1100011100011
110001111010X
100001100
n3n2n1n0
110001111011X
110001101i3i2i1i0
1100011100100
111001100
n3n2n1n0
1100011100101
111001101
n3n2n1n0
1100011100110
111001110
n3n2n1n0
1100011100111
111001111
n3n2n1n0
1100011101000
1100011101100
111000100
n3n2n1n0
110001000i3i2i1i0
111000000
n3n2n1n0
1100011101001
1100011101101
111000101
n3n2n1n0
110001001i3i2i1i0
111000001
n3n2n1n0
1100011101010
1100011101110
111000110
n3n2n1n0
110001010i3i2i1i0
111000010
n3n2n1n0
1100011101011
1100011101111
111000111
n3n2n1n0
110001011i3i2i1i0
111000011
n3n2n1n0
10110i1i0
a5a4a3a2a1a0
10111i1i0
a5a4a3a2a1a0
1000011110000
1000011110100
2 ×
2 ↓ ––– ×
1 ↓ – ×
1 ↓ – ×
2 ↓ – ●
2 ↓ – ×
2 ↓ – ●
2 ↓ – ×
1 ↓ – ×
1 ↓ – ×
2 ↓ – ●
2 ↓ – ×
2 ↓ – ●
2 ↓ – ×
1 ↓ – ×
1 ↓ – ×
1 ↓ – ×
1 ↓ – ●
1 ↓ – ×
1 ↓ – ●
1 ↓ – ×
1 ↓ – ×
2 ↓ – ×
1 ↓ – ×
1 ↓ – ×
1 ↓ – ●
2 ↓ – ●
1 ↓ – ×
2 ↓ – ×
1 ↓ – ●
2 ↓ – ●
1 ↓ – ×
2 ↓ – ×
2 ↓ – ●
2 ↓ – ●
2 ↓ – ●
2 ↓ – ●
2 ↓ – ●
2 ↓ – ×
2 ↓ – ×
2 ↓ – ×
2 ↓ – ×
2 ↓ – ×
2 ↓ – ●
2 ↓ – ●
2 ↓ – ●
2 ↓ – ●
2 ↓ – ●
2 ↓ – ×
2 ↓ – ×
2 ↓ – ×
2 ↓ – ×
2 ↓ – ×
2 ↓ –– ×
2 ↓ –– ×
1 ↓ – ×
1 ↓ – ×
↔↔
PC ← ([SP1∗4+3]~[SP1∗4]), SP1 ← SP1+1
F ← [SP2], SP2 ← SP2+1
PC ← ([SP1∗4+3]~[SP1∗4]), SP1 ← SP1+1
PC ← PC+1
A (C←D3←D2←D1←D0←C)
B (C←D3←D2←D1←D0←C)
[X] (C←D3←D2←D1←D0←C)
[X] (C←D3←D2←D1←D0←C), X ← X+1
[Y] (C←D3←D2←D1←D0←C)
[Y] (C←D3←D2←D1←D0←C), Y ← Y+1
A (C→D3→D2→D1→D0→C)
B (C→D3→D2→D1→D0→C)
[X] (C→D3→D2→D1→D0→C)
[X] (C→D3→D2→D1→D0→C), X ← X+1
[Y] (C→D3→D2→D1→D0→C)
[Y] (C→D3→D2→D1→D0→C), Y ← Y+1
A ← A-A-C
A ← A-B-C
A ← A-imm4-C
A ← A-[X]-C
A ← A-[X]-C, X ← X+1
A ← A-[Y]-C
A ← A-[Y]-C, Y ← Y+1
B ← B-A-C
B ← N's adjust (B-A-C)
B ← B-B-C
B ← B-imm4-C
B ← B-[X]-C
B ← N's adjust (B-[X]-C)
B ← B-[X]-C, X ← X+1
B ← N's adjust (B-[X]-C), X ← X+1
B ← B-[Y]-C
B ← N's adjust (B-[Y]-C)
B ← B-[Y]-C, Y ← Y+1
B ← N's adjust (B-[Y]-C), Y ← Y+1
[X] ← [X]-A-C
[X] ← [X]-B-C
[X] ← N's adjust ([X]-B-C)
[X] ← [X]-imm4-C
[X] ← N's adjust ([X]-0-C)
[X] ← [X]-A-C, X ← X+1
[X] ← [X]-B-C, X ← X+1
[X] ← N's adjust ([X]-B-C), X ← X+1
[X] ← [X]-imm4-C, X ← X+1
[X] ← N's adjust ([X]-0-C), X ← X+1
[Y] ← [Y]-A-C
[Y] ← [Y]-B-C
[Y] ← N's adjust ([Y]-B-C)
[Y] ← [Y]-imm4-C
[Y] ← N's adjust ([Y]-0-C)
[Y] ← [Y]-A-C, Y ← Y+1
[Y] ← [Y]-B-C, Y ← Y+1
[Y] ← N's adjust ([Y]-B-C), Y ← Y+1
[Y] ← [Y]-imm4-C, Y ← Y+1
[Y] ← N's adjust ([Y]-0-C), Y ← Y+1
[00addr6] ← [00addr6]
∨
(2
imm2
)
[FFaddr6] ← [FFaddr6]
∨
(2
imm2
)
A (C←D3←D2←D1←D0←0)
B (C←D3←D2←D1←D0←0)
Mnemonic
Machine code
Operation Cycle Page
Flag EXT.
mode
12
EICZ
11109876543210
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