24888 Rev 3.03 - July 12, 2004 AMD-8151
TM
AGP Tunnel Data Sheet
44
NAND tree 1: output signal is STRAPL[5]. However, the gate connected to the last signal in this NAND tree
(LDTCOMP[3]) is an AND gate rather than a NAND gate; so the expected output of this NAND tree is
inverted compared to the other NAND trees.
NAND tree 2: output signal is STRAPL[4].
1 LRBCLK0_[P,N] 11 LTBCLK0_P 21 LTBCAD_P[4] 31 LDTCOMP[2]
2 LRBCAD_[P,N][0] 12 LTBCLK0_N 22 LTBCAD_N[4] 32 LDTCOMP[3]
3 LRBCAD_[P,N][1] 13 LTBCAD_P[0] 23 LTBCAD_P[5]
4 LRBCAD_[P,N][2] 14 LTBCAD_N[0] 24 LTBCAD_N[5]
5 LRBCAD_[P,N][3] 15 LTBCAD_P[1] 25 LTBCAD_P[6]
6 LRBCAD_[P,N][4] 16 LTBCAD_N[1] 26 LTBCAD_N[6]
7 LRBCAD_[P,N][5] 17 LTBCAD_P[2] 27 LTBCAD_P[7]
8 LRBCAD_[P,N][6] 18 LTBCAD_N[2] 28 LTBCAD_N[7]
9 LRBCAD_[P,N][7] 19 LTBCAD_P[3] 29 LTBCTL_P
10 LRBCTL_[P,N] 20 LTBCAD_N[3] 30 LTBCTL_N
1 LRACLK0_[P,N] 21 LTACLK0_N 41 LTACAD_N[4]
2 LRACLK1_[P,N] 22 LTACLK1_P 42 LTACAD_P[12]
3 LRACAD_[P,N][0] 23 LTACLK1_N 43 LTACAD_N[12]
4 LRACAD_[P,N][8] 24 LTACAD_P[0] 44 LTACAD_P[5]
5 LRACAD_[P,N][1] 25 LTACAD_N[0] 45 LTACAD_N[5]
6 LRACAD_[P,N][9] 26 LTACAD_P[8] 46 LTACAD_P[13]
7 LRACAD_[P,N][2] 27 LTACAD_N[8] 47 LTACAD_N[13]
8 LRACAD_[P,N][10] 28 LTACAD_P[1] 48 LTACAD_P[6]
9 LRACAD_[P,N][3] 29 LTACAD_N[1] 49 LTACAD_N[6]
10 LRACAD_[P,N][11] 30 LTACAD_P[9] 50 LTACAD_P[14]
11 LRACAD_[P,N][4] 31 LTACAD_N[9] 51 LTACAD_N[14]
12 LRACAD_[P,N][12] 32 LTACAD_P[2] 52 LTACAD_P[7]
13 LRACAD_[P,N][5] 33 LTACAD_N[2] 53 LTACAD_N[7]
14 LRACAD_[P,N][13] 34 LTACAD_P[10] 54 LTACAD_P[15]
15 LRACAD_[P,N][6] 35 LTACAD_N[10] 55 LTACAD_N[15]
16 LRACAD_[P,N][14] 36 LTACAD_P[3] 56 LTACTL_P
17 LRACAD_[P,N][7] 37 LTACAD_N[3] 57 LTACTL_N
18 LRACAD_[P,N][15] 38 LTACAD_P[11]
19 LRACTL_[P,N] 39 LTACAD_N[11]
20 LTACLK0_P 40 LTACAD_P[4]
