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DRAWING NO.
DRAWING TITLE
DATE
Filename:
ECO No. DESCRIPTION OF CHANGE
AVD RECLOCKING.SCH
AV8 Reclocking
Contact Engineer:
L896CT
1-Aug-2002
INITIALS
Printed:
11 11Sheet of
Notes:
Contact Tel: (01223) 203200EngName A Dutton
A & R Cambridge Ltd.
Pembroke Avenue
Cambridge CB5 9PB
Waterbeach
23425
DAC I2S DATA LR
1OE
1
1A0
2
2Y0
3
1A1
4
2Y1
5
1A2
6
2Y2
7
1A3
8
2Y3
9
GND
10
2A3
11
1Y3
12
2A2
13
1Y2
14
2A1
15
1Y1
16
2A0
17
1Y0
18
2OE
19
VCC
20
IC1100
74LVC244AD
DAC I2S DATA CS
DAC I2S DATA LSRS
DAC I2S DATA LSBRSB
DGND
C1103
100N 0805
DAC I2S BCLK LR
DAC I2S BCLK CS
DAC I2S BCLK LSRS
DAC I2S BCLK LSBRSB
DAC I2S LRCLK LR
DAC I2S LRCLK CS
DAC I2S LRCLK LSRS
DAC I2S LRCLK LSBRSB
1
2
3
4 5
6
7
8
RP1101
100R X 4 ISO
1
2
3
45
6
7
8
RP1100
100R X 4 ISO
R1100
100R 0805
PSU SYNC BCLK
70R@100MHz
L1101
7F004
DGND DGND
P3V3D
C1100
100N 0805
PSU SYNC BCLK
1
2
3
45
6
7
8
RP1102
100R X 4 ISO
1
2
3
4 5
6
7
8
CP1100
100P X 4 ISO
1
2
3
4 5
6
7
8
CP1101
100P X 4 ISO
1
2
3
4 5
6
7
8
CP1102
100P X 4 ISO
DGND
DGND
DSP2 BCLK
DSP2 LRCLK
DATA LR
DATA CS
DATA LSRS
DATA LSBRSB
RCLK MCLK
MR
1
Q0
2
D0
3
D1
4
Q1
5
D2
6
Q2
7
GND
8
CP
9
Q3
10
D3
11
Q4
12
D4
13
D5
14
Q5
15
VCC
16
IC1102
74LV174 D SM
DGND
C1104
100N 0805
70R@100MHz
L1100
7F004
DGND DGND
P3V3D
C1101
100N 0805
1
2
3
4
5
6
7
8
SK1100
AMPCT8
R1101
100R 0805 1%
R1102
100R 0805 1%
DGND
DSP2 BCLK
DSP2 LRCLK
DATA LR
DATA CS
DATA LSRS
DATA LSBRSB
1
2
3
4
5
6
7
8
SK1101
AMPCT8
DGND
WAF 12/02/02 1.202_E044
R701 TO R704 & R708 TO R711 CHANGED TO 3K3 IC104 UPDATED
C200, C201 & C228 changed from 10U 35V to 100U 16V R911 TO 10K
02_101 WF/AD 16/5/02 IC906 FROM 5G24LC08 TO 5G24LC16 TO GIVE MORE SPACE 1.3.0
02_E127 AD 27/06/02 Remove R803 for PLL board upgrade 1.4.0
02_E160 WAF 27/06/02 R921 FROM 10K TO 33K 1.5.0
02_E161 WAF 1/8/02 CHANGES TO SOME PHASE LOCKED LOOP COMPS AND IC907 1.6.0